User`s manual

Chapter 2
20
2.8 JP20 - CPU CLOCK DELAY
JP20 is for the CPU Clock Delay setting. Refer to Fig 2 for JP20 location.
JP20 -- CPU Clock Delay
2.9 JP5, JP6, JP7 - CPU FREQUENCY CONFIGURATION
JP5, JP6, & JP7 are for the CPU Frequency Configuration. Two different settings are provided for
different Clock Generator that is used at U16 or U17. Refer to Fig 2 for the location of U16/U17 and
jumpers.
JP5, JP6, JP7-- CPU Frequency Configuration
Note:
Winbond W83C17 and UMC U59515-01 are pin to pin compatible to MX-8315 and
PhaseLink PLL52C08-01 is pin to pin compatible to AV9107-03.
Table 7
Table 8