Data Sheet
Revision 2.0  Page 58 of 74
nRF24L01 Product Specification
 Table 24. Register map of nRF24L01
N/A RX_PLD 255:0 X R Read by separate SPI command
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO with 
three levels.
All RX channels share the same FIFO
1C
DYNPD
c
Enable dynamic payload length
Reserved 7:6 0 R/W Only ‘00’ allowed
DPL_P5 5 0 R/W Enable dyn. payload length data pipe 5. 
(Requires EN_DPL and ENAA_P5)
DPL_P4 4 0 R/W Enable dyn. payload length data pipe 4. 
(Requires EN_DPL and ENAA_P4)
DPL_P3 3 0 R/W Enable dyn. payload length data pipe 3. 
(Requires EN_DPL and ENAA_P3)
DPL_P2 2 0 R/W Enable dyn. payload length data pipe 2. 
(Requires EN_DPL and ENAA_P2)
DPL_P1 1 0 R/W Enable dyn. payload length data pipe 1. 
(Requires EN_DPL and ENAA_P1)
DPL_P0 0 0 R/W Enable dyn. payload length data pipe 0. 
(Requires EN_DPL and ENAA_P0)
1D
FEATURE
c
R/W Feature Register
Reserved 7:3 0 R/W Only ‘00000’ allowed
EN_DPL 2 0 R/W Enables Dynamic Payload Length
EN_ACK_PAY
d
1 0 R/W Enables Payload with ACK
EN_DYN_ACK 0 0 R/W Enables the W_TX_PAYLOAD_NOACK command
a. This is the time the PTX is waiting for an ACK packet before a retransmit is made. The PTX is in RX mode 
for a minimum of 250µS, but it stays in RX mode to the end of the packet if that is longer than 250µS. Then 
it goes to standby-I mode for the rest of the specified ARD. After the ARD it goes to TX mode and then 
retransmits the packet. 
b. The 
RX_DR IRQ is asserted by a new packet arrival event. The procedure for handling this interrupt 
should be: 1) read payload through SPI, 2) clear 
RX_DR IRQ, 3) read FIFO_STATUS to check if there 
are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat from 1)
c. To activate this feature use the 
ACTIVATE SPI command followed by data 0x73. The corresponding bits 
in the 
FEATURE register must be set.
d. If ACK packet payload is activated, ACK packets have dynamic payload lengths and the Dynamic Pay-
load Length feature should be enabled for pipe 0 on the PTX and PRX. This is to ensure that they receive 
the ACK packets with payloads. If the payload in ACK is more than 15 byte in 2Mbps mode the ARD must 
be 500µS or more, and if the payload is more than 5byte in 1Mbps mode the ARD must be 500µS or more.
Address 
(Hex)
Mnemonic Bit
Reset 
Value
Type Description










