Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 80 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.
To send more than one data stream NSS must be set HIGH between the data streams.
Fig 25. Timing diagram for SPI
Fig 26. Timing for Fast and Standard mode devices on the I
2
C-bus
001aaj634
t
SCKL
t
SCKH
t
SCKL
t
DXSH
t
SHDX
t
DXSH
t
SLDX
t
SLNH
MOSI
SCK
MISO
MSB
MSB
LSB
LSB
NSS
001aaj635
SDA
t
f
SCL
t
LOW
t
f
t
SP
t
r
t
HD;STA
t
HD;DAT
t
HD;STA
t
r
t
HIGH
t
SU;DAT
SSrPS
t
SU;STA
t
SU;STO
t
BUF