Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 69 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
Table 141. Reserved register (address 3Ch); reset value: FFh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RFT
Access -
Table 142. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for production tests
Table 143. Reserved register (address 3Dh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RFT
Access -
Table 144. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for production tests
Table 145. Reserved register (address 3Eh); reset value: 03h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RFT
Access -
Table 146. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for production tests
Table 147. Reserved register (address 3Fh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 148. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for production tests