Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 67 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.4.9 AnalogTestReg register
Determines the analog output test signal at, and status of, pins AUX1 and AUX2.
[1] Remark: Current source output; the use of 1 k pull-down resistor on AUXn is recommended.
Table 133. AnalogTestReg register (address 38h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol AnalogSelAux1[3:0] AnalogSelAux2[3:0]
Access R/W R/W
Table 134. AnalogTestReg register bit descriptions
Bit Symbol Value Description
7 to 4 AnalogSelAux1
[3:0]
controls pin AUX1
0000 3-state
0001 output of TestDAC1 (AUX1), output of TestDAC2 (AUX2)
[1]
0010 test signal Corr1
[1]
0011 reserved
0100 DAC: test signal MinLevel
[1]
0101 DAC: test signal ADC_I
[1]
0110 DAC: test signal ADC_Q
[1]
0111 reserved
1000 reserved, test signal for production test
[1]
1001 reserved
1010 HIGH
1011 LOW
1100 TxActive:
at 106 kBd: HIGH during Start bit, Data bit, Parity and CRC
at 212 kBd: 424 kBd and 848 kBd: HIGH during data and
CRC
1101 RxActive:
at 106 kBd: HIGH during Data bit, Parity and CRC
at 212 kBd: 424 kBd and 848 kBd: HIGH during data and
CRC
1110 subcarrier detected:
106 kBd: not applicable
212 kBd: 424 kBd and 848 kBd: HIGH during last part of
data and CRC
1111 test bus bit as defined by the TestSel1Reg register’s
TstBusBitSel[2:0] bits
Remark: all test signals are described in Section 16.1 on
page 82
3 to 0 AnalogSelAux2
[3:0]
- controls pin AUX2 (see bit descriptions for AUX1)