Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 66 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.4.7 AutoTestReg register
Controls the digital self-test.
9.3.4.8 VersionReg register
Shows the MFRC522 software version.
MFRC522 version 1.0 software version is: 91h.
MFRC522 version 2.0 software version is: 92h.
Table 128. TestBusReg register bit descriptions
Bit Symbol Description
7 to 0 TestBus[7:0] shows the status of the internal test bus
the test bus is selected using the TestSel2Reg register; see
Section 16.1 on page 82
Table 129. AutoTestReg register (address 36h); reset value: 40h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved AmpRcv RFT SelfTest[3:0]
Access - R/W - R/W
Table 130. AutoTestReg register bit descriptions
Bit Symbol Value Description
7 reserved - reserved for production tests
6 AmpRcv 1 internal signal processing in the receiver chain is performed
non-linearly which increases the operating distance in
communication modes at 106 kBd
Remark: due to non-linearity, the effect of the RxThresholdReg
register’s MinLevel[3:0] and the CollLevel[2:0] values is also
non-linear
5 to 4 RFT - reserved for production tests
3 to 0 SelfTest[3:0] - enables the digital self test
the self test can also be started by the CalcCRC command; see
Section 10.3.1.4 on page 71
the self test is enabled by value 1001b
Remark: for default operation the self test must be disabled
by value 0000b
Table 131. VersionReg register (address 37h); reset value: xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol Version[7:0]
Access R
Table 132. VersionReg register bit descriptions
Bit Symbol Description
7 to 4 Chiptype ‘9’ stands for MFRC522
3 to 0 Version ‘1’ stands for MFRC522 version 1.0 and ‘2’ stands for MFRC522
version 2.0.