Data Sheet

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Product data sheet

COMPANY PUBLIC

Rev. 3.9 — 27 April 2016

112139 65 of 95

NXP Semiconductors

MFRC522

Standard performance MIFARE and NTAG frontend

9.3.4.5 TestPinValueReg register

Defines the HIGH and LOW values for the test port D1 to D7 when it is used as I/O.

9.3.4.6 TestBusReg register

Shows the status of the internal test bus.

Table 124. TestPinEnReg register bit descriptions

Bit Symbol Value Description

7 RS232LineEn 0 serial UART lines MX and DTRQ are disabled

6 to 1 TestPinEn

[5:0]

- enables the output driver on one of the data pins D1 to D7 which

outputs a test signal

Example:

setting bit 1 to logic 1 enables pin D1 output

setting bit 5 to logic 1 enables pin D5 output

Remark: If the SPI is used, only pins D1 to D4 can be used. If the

serial UART interface is used and the RS232LineEn bit is set to

logic 1 only pins D1 to D4 can be used.

0 reserved - reserved for future use

Table 125. TestPinValueReg register (address 34h); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol UseIO TestPinValue[5:0] reserved

Access R/W R/W -

Table 126. TestPinValueReg register bit descriptions

Bit Symbol Value Description

7 UseIO 1 enables the I/O functionality for the test port when one of the serial

interfaces is used

the input/output behavior is defined by value TestPinEn[5:0] in the

TestPinEnReg register

the value for the output behavior is defined by TestPinValue[5:0]

6 to 1 TestPinValue

[5:0]

- defines the value of the test port when it is used as I/O and each

output must be enabled by TestPinEn[5:0] in the TestPinEnReg

Remark: Reading the register indicates the status of pins D6 to D1

if the UseIO bit is set to logic 1. If the UseIO bit is set to logic 0, the

value of the TestPinValueReg register is read back.

0 reserved - reserved for future use

Table 127. TestBusReg register (address 35h); reset value: xxh bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol TestBus[7:0]

Access R