Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 63 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.4 Page 3: Test
9.3.4.1 Reserved register 30h
Functionality is reserved for future use.
9.3.4.2 TestSel1Reg register
General test signal configuration.
Table 113. TCounterValReg (higher bits) register (address 2Eh); reset value: xxh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol TCounterVal_Hi[7:0]
Access R
Table 114. TCounterValReg register higher bit descriptions
Bit Symbol Description
7 to 0 TCounterVal_Hi
[7:0]
timer value higher 8 bits
Table 115. TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol TCounterVal_Lo[7:0]
Access R
Table 116. TCounterValReg register lower bit descriptions
Bit Symbol Description
7 to 0 TCounterVal_Lo
[7:0]
timer value lower 8 bits
Table 117. Reserved register (address 30h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 118. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for future use
Table 119. TestSel1Reg register (address 31h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved TstBusBitSel[2:0]
Access - R/W