Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 6 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
7. Pinning information
7.1 Pin description
Fig 3. Pinning configuration HVQFN32 (SOT617-1)
001aaj819
MFRC522
Transparent top view
RX
MFIN
MFOUT
AVSS
NRSTPD AUX1
PVSS AUX2
DVSS OSCIN
DVDD OSCOUT
PVDD IRQ
I2C SDA/NSS/RX
SVDD
TVSS
TX1
TVDD
TX2
TVSS
AVDD
VMID
EA D7/SCL/MISO/TX D6/ADR_0/MOSI/MX D5/ADR_1/SCK/DTRQ D4/ADR_2 D3/ADR_3 D2/ADR_4 D1/ADR_5
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
Table 3. Pin description
Pin Symbol Type
[1]
Description
1I2C II
2
C-bus enable input
[2]
2 PVDD P pin power supply
3 DVDD P digital power supply
4 DVSS G digital ground
[3]
5 PVSS G pin power supply ground
6 NRSTPD I reset and power-down input:
power-down: enabled when LOW; internal current sinks are switched off, the oscillator
is inhibited and the input pins are disconnected from the outside world
reset: enabled by a positive edge
7 MFIN I MIFARE signal input
8 MFOUT O MIFARE signal output
9 SVDD P MFIN and MFOUT pin power supply
10 TVSS G transmitter output stage 1 ground
11 TX1 O transmitter 1 modulated 13.56 MHz energy carrier output
12 TVDD P transmitter power supply: supplies the output stage of transmitters 1 and 2
13 TX2 O transmitter 2 modulated 13.56 MHz energy carrier output
14 TVSS G transmitter output stage 2 ground
15 AVDD P analog power supply