Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 55 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.2.14 MfRxReg register
9.3.2.15 Reserved register 1Eh
Functionality is reserved for future use.
9.3.2.16 SerialSpeedReg register
Selects the speed of the serial UART interface.
Table 77. MfTxReg register (address 1Ch); reset value: 62h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved TxWait[1:0]
Access - R/W
Table 78. MfTxReg register bit descriptions
Bit Symbol Description
7 to 2 reserved reserved for future use
1 to 0 TxWait defines the additional response time
7 bits are added to the value of the register bit by default
Table 79. MfRxReg register (address 1Dh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved ParityDisable reserved
Access - R/W -
Table 80. MfRxReg register bit descriptions
Bit Symbol Value Description
7 to 5 reserved - reserved for future use
4 ParityDisable 1 generation of the parity bit for transmission and the parity check for
receiving is switched off
the received parity bit is handled like a data bit
3 to 0 reserved - reserved for future use
Table 81. Reserved register (address 1Eh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 82. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for future use
Table 83. SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol BR_T0[2:0] BR_T1[4:0]
Access R/W R/W