Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 54 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.2.11 Reserved register 1Ah
Functionality is reserved for future use.
9.3.2.12 Reserved register 1Bh
Functionality is reserved for future use.
9.3.2.13 MfTxReg register
Controls some MIFARE communication transmit parameters.
4 TPrescalEven R/W Available on RC522 version 1.0 and version 2.0:
If set to logic 0 the following formula is used to calculate the timer
frequency of the prescaler:
f
timer
= 13.56 MHz / (2*TPreScaler+1).
Only available on version 2.0:
If set to logic 1 the following formula is used to calculate the timer
frequency of the prescaler:
f
timer
= 13.56 MHz / (2*TPreScaler+2).
Default TPrescalEven bit is logic 0, find more information on the
prescaler in Section 8.5
.
3 to 2 TauRcv[1:0] - changes the time-constant of the internal PLL during data
reception
Remark: if set to 00b the PLL is frozen during data reception
1 to 0 TauSync[1:0] - changes the time-constant of the internal PLL during burst
Table 72. DemodReg register bit descriptions
…continued
Bit Symbol Value Description
Table 73. Reserved register (address 1Ah); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 74. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for future use
Table 75. Reserved register (address 1Bh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 76. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for future use