Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 49 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.2.4 RxModeReg register
Defines the data rate during reception.
Table 58. TxModeReg register bit descriptions
Bit Symbol Value Description
7 TxCRCEn 1 enables CRC generation during data transmission
Remark: can only be set to logic 0 at 106 kBd
6 to 4 TxSpeed[2:0] defines the bit rate during data transmission
the MFRC522 handles transfer speeds up to
848 kBd
000 106 kBd
001 212 kBd
010 424 kBd
011 848 kBd
100 reserved
101 reserved
110 reserved
111 reserved
3 InvMod 1 modulation of transmitted data is inverted
2 to 0 reserved - reserved for future use
Table 59. RxModeReg register (address 13h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RxCRCEn RxSpeed[2:0] RxNoErr RxMultiple reserved
Access R/W D R/W R/W -
Table 60. RxModeReg register bit descriptions
Bit Symbol Value Description
7 RxCRCEn 1 enables the CRC calculation during reception
Remark: can only be set to logic 0 at 106 kBd
6 to 4 RxSpeed[2:0] defines the bit rate while receiving data
the MFRC522 handles transfer speeds up to 848 kBd
000 106 kBd
001 212 kBd
010 424 kBd
011 848 kBd
100 reserved
101 reserved
110 reserved
111 reserved
3 RxNoErr 1 an invalid received data stream (less than 4 bits received) will
be ignored and the receiver remains active