Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 47 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.1.16 Reserved register 0Fh
Functionality is reserved for future use.
9.3.2 Page 1: Communication
9.3.2.1 Reserved register 10h
Functionality is reserved for future use.
4 to 0 CollPos[4:0] - shows the bit position of the first detected collision in a
received frame
only data bits are interpreted
example:
00h indicates a bit-collision in the 32
nd
bit
01h indicates a bit-collision in the 1
st
bit
08h indicates a bit-collision in the 8
th
bit
These bits will only be interpreted if the
CollPosNotValid bit is set to logic 0
Table 50. CollReg register bit descriptions …continued
Bit Symbol Value Description
Table 51. Reserved register (address 0Fh); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 52. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for future use
Table 53. Reserved register (address 10h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol reserved
Access -
Table 54. Reserved register bit descriptions
Bit Symbol Description
7 to 0 reserved reserved for future use