Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 45 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.1.13 ControlReg register
Miscellaneous control bits.
Table 44. WaterLevelReg register bit descriptions
Bit Symbol Description
7 to 6 reserved reserved for future use
5 to 0 WaterLevel
[5:0]
defines a warning level to indicate a FIFO buffer overflow or underflow:
Status1Reg register’s HiAlert bit is set to logic 1 if the remaining
number of bytes in the FIFO buffer space is equal to, or less than the
defined number of WaterLevel bytes
Status1Reg register’s LoAlert bit is set to logic 1 if equal to, or less
than the WaterLevel bytes in the FIFO buffer
Remark: to calculate values for HiAlert and LoAlert see
Section 9.3.1.8 on page 42
.
Table 45. ControlReg register (address 0Ch); reset value: 10h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TStopNow TStartNow reserved RxLastBits[2:0]
Access W W - R
Table 46. ControlReg register bit descriptions
Bit Symbol Value Description
7 TStopNow 1 timer stops immediately
reading this bit always returns it to logic0
6 TStartNow 1 timer starts immediately
reading this bit always returns it to logic 0
5 to 3 reserved - reserved for future use
2 to 0 RxLastBits[2:0] - indicates the number of valid bits in the last received byte
if this value is 000b, the whole byte is valid