Data Sheet

MFRC522 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.9 — 27 April 2016
112139 39 of 95
NXP Semiconductors
MFRC522
Standard performance MIFARE and NTAG frontend
9.3.1.4 DivIEnReg register
Control bits to enable and disable the passing of interrupt requests.
9.3.1.5 ComIrqReg register
Interrupt request bits.
Table 26. ComIEnReg register bit descriptions
Bit Symbol Value Description
7 IRqInv 1 signal on pin IRQ is inverted with respect to the Status1Reg register’s
IRq bit
0 signal on pin IRQ is equal to the IRq bit; in combination with the
DivIEnReg register’s IRqPushPull bit, the default value of logic 1 ensures
that the output level on pin IRQ is 3-state
6 TxIEn - allows the transmitter interrupt request (TxIRq bit) to be propagated to
pin IRQ
5 RxIEn - allows the receiver interrupt request (RxIRq bit) to be propagated to pin
IRQ
4 IdleIEn - allows the idle interrupt request (IdleIRq bit) to be propagated to pin IRQ
3 HiAlertIEn - allows the high alert interrupt request (HiAlertIRq bit) to be propagated to
pin IRQ
2 LoAlertIEn - allows the low alert interrupt request (LoAlertIRq bit) to be propagated to
pin IRQ
1 ErrIEn - allows the error interrupt request (ErrIRq bit) to be propagated to pin IRQ
0 TimerIEn - allows the timer interrupt request (TimerIRq bit) to be propagated to pin
IRQ
Table 27. DivIEnReg register (address 03h); reset value: 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IRQPushPull reserved MfinActIEn reserved CRCIEn reserved
Access R/W - R/W - R/W -
Table 28. DivIEnReg register bit descriptions
Bit Symbol Value Description
7 IRQPushPull 1 pin IRQ is a standard CMOS output pin
0 pin IRQ is an open-drain output pin
6 to 5 reserved - reserved for future use
4 MfinActIEn - allows the MFIN active interrupt request to be propagated to
pin IRQ
3 reserved - reserved for future use
2 CRCIEn - allows the CRC interrupt request, indicated by the DivIrqReg
register’s CRCIRq bit, to be propagated to pin IRQ
1 to 0 reserved - reserved for future use
Table 29. ComIrqReg register (address 04h); reset value: 14h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Access W D D D D D D D