Data Sheet

Product data sheet

COMPANY PUBLIC

Rev. 3.9 — 27 April 2016

112139 11 of 95

NXP Semiconductors

MFRC522

Standard performance MIFARE and NTAG frontend

8.1.2.2 SPI write data

To write data to the MFRC522 using SPI requires the byte order shown in Table 7

. It is

possible to write up to n data bytes by only sending one address byte.

The first send byte defines both the mode and the address byte.

[1] X = Do not care.

Remark: The MSB must be sent first.

8.1.2.3 SPI address byte

The address byte must meet the following format.

The MSB of the first byte defines the mode used. To read data from the MFRC522 the

MSB is set to logic 1. To write data to the MFRC522 the MSB must be set to logic 0. Bits 6

to 1 define the address and the LSB is set to logic 0.

8.1.3 UART interface

8.1.3.1 Connection to a host

Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s

RS232LineEn bit.

Table 7. MOSI and MISO byte order

Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1

MOSI address 0 data 0 data 1 ... data n  1data n

MISO X

[1]

... X

[1]

Table 8. Address byte 0 register; address MOSI

7 (MSB) 6 5 4 3 2 1 0 (LSB)

1 = read

0 = write

address 0

Fig 8. UART connection to microcontrollers

001aak587

MFRC522

DTRQ