Data Sheet

Revision 2.0 Page 57 of 74
nRF24L01 Product Specification
RX_PW_P4 5:0 0 R/W Number of bytes in RX payload in data pipe 4 (1
to 32 bytes).
0 Pipe not used
1 = 1 byte
32 = 32 bytes
16 RX_PW_P5
Reserved 7:6 00 R/W Only '00' allowed
RX_PW_P5 5:0 0 R/W Number of bytes in RX payload in data pipe 5 (1
to 32 bytes).
0 Pipe not used
1 = 1 byte
32 = 32 bytes
17 FIFO_STATUS FIFO Status Register
Reserved 7 0 R/W Only '0' allowed
TX_REUSE 6 0 R Reuse last transmitted data packet if set high.
The packet is repeatedly retransmitted as long
as CE is high. TX_REUSE is set by the SPI com-
mand REUSE_TX_PL, and is reset by the SPI
commands W_TX_PAYLOAD or FLUSH TX
TX_FULL 5 0 R TX FIFO full flag. 1: TX FIFO full. 0: Available
locations in TX FIFO.
TX_EMPTY 4 1 R TX FIFO empty flag.
1: TX FIFO empty.
0: Data in TX FIFO.
Reserved 3:2 00 R/W Only '00' allowed
RX_FULL 1 0 R RX FIFO full flag.
1: RX FIFO full.
0: Available locations in RX FIFO.
RX_EMPTY 0 1 R RX FIFO empty flag.
1: RX FIFO empty.
0: Data in RX FIFO.
N/A
ACK_PLD
c
255:0 X W Written by separate SPI command
ACK packet payload to data pipe number PPP
given in SPI command
Used in RX mode only
Maximum three ACK packet payloads can be
pending. Payloads with same PPP are handled
first in first out.
N/A TX_PLD 255:0 X W Written by separate SPI command TX data pay-
load register 1 - 32 bytes.
This register is implemented as a FIFO with
three levels.
Used in TX mode only
Address
(Hex)
Mnemonic Bit
Reset
Value
Type Description