Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 89

UG111 (v1.4) January 30, 2004 1-800-255-7778

Importing an Existing Peripheral

Please ensure that filename does not have any spaces. Such path names are not supported

at the present time.

The top-level HDL source file is expected to conform to the Xilinx implementation of the

CoreConnect Bus Conventions. Please review OPB/PLB usage in Chapter 1 and 2 of the

Processor IP User Guide found in the doc directory in the install.

HDL Analysis Information

In this panel you indicate compile order of your HDL files and the logical libraries they are

compiled into.

If you had chosen to select your HDL source files by parsing the XST project file, then this

panel would contain the list of files and the logical libraries they are compiled into. You are

not allowed to modify the file-names and ordering if the given XST project file contains the

‘nosort’ keyword.

Figure 4-11: Choose HDL Source Files

Figure 4-12: Intuiting HDL Analysis Information from XST Project Files