Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 87
UG111 (v1.4) January 30, 2004 1-800-255-7778
Importing an Existing Peripheral
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understand how to address the registers and interpret the data available there. These are
documented in the IPIF section of the Processor IP Document. You should create a simple
test system and implement and simulate that using the various flows available in the EDK.
Generating the files representing your peripheral
Once all the required data has been collected from the user, this tool does the following:
x Creates HDL files described above.
x Creates other files that help you complete the implementation of user_logic.vhd.
These files include elements that help you design the peripheral using ISE, and other
documentation files that help you write applications using this core.
If you already have any files in the target area, they will be overwritten.
Note that this tool is highly dependent on the port/parameter interface and the set of HDL
files that comprise your peripherals. If these change during implementation, you will have
to re-run this tool in the Import mode to regenerate the EDK interface files.
Importing an Existing Peripheral
This tool can import an existing peripheral.Your peripheral must be written in Verilog or
VHDL. It should also implement the Xilinx implementation of the CoreConnect bus
conventions. This tool is easiest to use if you have followed the naming conventions for the
ports and parameters. If not, it gives you the opportunity to establish the mapping of your
ports and peripherals to the ports and peripherals in the Xilinx implementation of the
CoreConnect bus conventions.
Generally, it is best to use this functionality in conjunction with the peripheral creation
functionality described in the “Creating New Peripherals” section.
In this mode, this tool does the following:
x Query the user about the characteristics of the peripheral and the location of the HDL
files that make up the peripheral. These include information about the CoreConnect
Bus that the peripheral is expected to be connected to, whether it is a master and/or
slave, the characteristics of the interrupts generated by the peripheral, etc.
x Copy out the HDL files into the XPS project or EDK repository using the rules for
creating XPS and EDK repositories.
x Generate interface files like the Microprocessor Peripheral Data (MPD), Peripheral
Analyze Order (PAO) and Black-box Data (BBD). These allow the tools in the EDK
instantiate your peripheral in a system being designed using XPS.
It is very important that you follow certain conventions when you design your peripheral.
The most important is the conventions used to name the top module and the logical library
it is compiled into.
The subsequent sections explain the functionality offered by this tool, and what you can do
with the files it generates.
Identifying the Physical Location of your Peripheral
This functionality is identical to what is described under “Identifying the Physical
Location of your Peripheral”in the “Creating New Peripherals” section.