Specifications

86 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 4: Create/Import Peripheral Wizard
R
Some of the IPIC ports in this panel are already selected and cannot be deselected. These
ports are required to implement the functionality indicated in the Select IPIF Services
panel.
Review EDK Peripheral Design Flow
After all the input has been entered, the following files are created:
x core_name.vhd
x user_logic.vhd
Here core_name.vhd implements the ‘top’ module core_name of your peripheral. It
instantiates the IPIF module from the built-in EDK cores library, and the user_logic
module. The bus-interface ports appear on this module. Internally, these ports are wired to
the IPIF module. The IPIF and user_logic modules are interconnected by the IPIC.
The user_logic module will usually have an empty implementation. In some cases a
simple implementation may be included, e.g. if software addressable register support is
requested, the user_logic.vhd implements simple read/write to software addressable
registers.
Generally, you will need to implement the user_logic module only. However, if your
user_logic module is not self-contained, and needs more interface ports, you will have
to add those to the core_name module in core_name.vhd. In such cases, just add the ports to
the core_name module and pass them through to the user_logic module. Do not make
any other changes to the core_name.vhd file.
Once you have completed the implementation of your peripheral, you need to import it
into XPS using this tool in the import mode. This will generate the XPS interface files and
run the HDL file set through a HDL parser to check for errors, etc.
It is very likely that you will implement user_logic.vhd using your favorite HDL based
design flow. This will require you to understand the IPIC protocol. Please refer to the
OPF_IPIF or PLB_IPIF chapter in the Processor IP document.
Once your user_logic.vhd is complete, you will want to put together a simple
processor system to ensure that the software and hardware component of your system are
interacting as expected. The software component of your system should implement the
register reads and writes required to test out the interface. To do this, you will need to
Figure 4-9: Review the EDK Peripheral Design Flow