Specifications

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processed in conjunction with the interrupts generated out of the other IPIF services. The
IP ISC has a software addressable interrupt enable register (IP IER) that may be used to
enable/disable interrupts from the software application. Both the IP ISC and ‘device’ ISC
are implemented in the IPIF component of the core.
In this panel, you will have to indicate the number of interrupts generated by the user-
logic, and the capture mode of these interrupts.
The following interrupt capture modes are supported:
x INTR_PASS_THRU
The interrupt from the user logic has no additional capture processing applied to it. It
is immediately sent to the IP ISC interrupt enable logic (IP IER) and thence to the
‘device’ ISC.
x INTR_PASS_THRU_INV
The input interrupt from the user logic is logically inverted but has no additional
capture processing applied to it. The inverted interrupt level is passed through the IP
IER and sent to the ‘device’ ISC interrupt enable logic. This mode is mainly used to
capture active- low interrupts.
x INTR_REG_EVENT
The IP ISC Status Register will sample the IP Interrupt input at the rising edge of each
bus clock pulse. If a logic high is sampled, the bit of the IP Interrupt Status Register
corresponding to the input interrupt position will stay high until the User Application
(ISR) clears the interrupt.
x INTR_REG_EVENT_INV
This capture mode is the same as the INTR_REG_EVENT mode except that the IP
Interrupt is logically inverted before it enters the sample and hold logic of the IP
interrupt status register.
x INTR_POS_EDGE_DETECT
The IP ISC Status Register will sample the interrupt input at the rising edge of each bus
clock pulse. A one bus clock delayed sample will also be maintained. The new sample
and the delayed sample will be compared. If the new sample is logic high and the old
sample is logic low (a rising edge event), the IP Interrupt Status Register will latch and
hold a logic ‘1’ for the interrupt bit position. Once latched, the bit of the IP Interrupt
Status Register corresponding to the input interrupt position will stay high until the
user application (interrupt service routine) clears the interrupt.
x INTR_NEG_EDGE_DETECT
The IP ISC Status Register will sample the interrupt input at the rising edge of each bus
clock pulse. A one bus clock delayed sample will also be maintained. The new sample
and the delayed sample will be compared. If the new sample is logic low and the old
sample is logic high (a falling edge event), the IP Interrupt Status Register will latch
and hold a logic ‘1’ for the interrupt bit position. Once latched, the bit of the IP
Interrupt Status Register corresponding to the input interrupt position will stay high
until the user application (interrupt service routine) clears the interrupt.
You will also have to indicate if you want to include the interrupts generated outside of the
user-logic block (in the other IPIF services) by checking the ‘Use Device ISC (Interrupt
Source Controller)’ check box. You can also choose to use the priority encoder service
offered by the IPIF. If the device interrupt service controller is not chosen, then only the
interrupts generated by the user-logic are recognized and processed through a user-logic
specific interrupt service controller.