Specifications

82 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 4: Create/Import Peripheral Wizard
R
Configure FIFOs
PLB peripherals has the option of using a FIFO available in the IPIF. (This would be
supported for OPB peripherals in a future release.)
In this panel, you choose to include a Read and/or Write FIFO. You also configure the FIFO
by indicating the number of entries it can store (i.e. its depth) and the size of each word
(byte, half-word, word or double.) Other features such as packet mode access and signals
that indicate FIFO vacancy, etc. can also be requested.
Configure Interrupt Handling
The peripheral will have a interrupt collection mechanism that manages the interrupts
generated by the user-logic and the IPIF services and generates a single interrupt line out
of the peripheral.
An addressable register based mechanism for enabling/disabling the interrupts generated
by the peripheral is provided, as are registers to determine the status and source of the
interrupts.
The interrupts generated by the user-logic part of the peripheral are first processed by a ‘IP
Interrupt Source Controller’ or ‘IP ISC’. The interrupt signal out of this controller is then
fed into the a ‘device interrupt source controller’ or ‘device ISC’ in the IPIF where they are
Include Software
Addressable Registers in
user-logic
The user-logic part of the peripheral will have registers
addressable through software.
Include Address Range
Support in user-logic
This will generate enable signals for each address range.
This feature is useful for peripherals that need to support
multiple address ranges, e.g. multiple memory banks. The
distinction between this and other cases is that the enable
signals are generated for each address range of the
address space supported by the peripheral, rather than for
each addressable register in the user-logic module.
Figure 4-5: Configure Interrupt Handling
Table 4-3: IPIF Services
IPIF Feature Description