Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 77

UG111 (v1.4) January 30, 2004 1-800-255-7778

Chapter 4

Create/Import Peripheral Wizard

The Xilinx Embedded Design Kit (EDK) comes with a large number of commonly used

peripherals. Many different kinds of systems can be created with these peripherals, but it is

likely that you may have to create your own custom peripheral to implement functionality

not available in the EDK peripherals library.

The Create/Import Peripheral Wizard helps you create your own peripherals and import

them into EDK compliant repositories or Xilinx Platform Studio (XPS) projects.

In the Create mode, this tool creates a number of files. Some of these files are templates

which will help you implement your peripheral without needing to have a detailed

understanding of the bus protocols, naming conventions or the formats of special interface

files required by the EDK.

In the Import mode, this tool will help you create the interface files and directory structures

that are necessary to make your peripheral visible to the various tools in the EDK. For this

mode of operation, it is assumed that you have followed the naming conventions required

by the EDK. Once imported, your peripheral will be like any other module available in the

EDK peripherals library.

These modes are described in the following sections:

x “Creating New Peripherals”

x “Importing an Existing Peripheral”

x “Limitations”

Creating New Peripherals

In this mode, this tool helps you create a peripheral suitable for instantiation into systems

designed using the EDK. You will have to answer a few simple questions and this tool will

output a number of HDL files that conform to the conventions and rules required by the

EDK. You will have to implement the body of one of the outputted HDL blocks. The

interface to this block is very generic: you will not have to fully understand the intricacies

of the CoreConnect bus protocol to implement your peripheral.

The current limitations of the tool include the following:

x Supports VHDL only

This is because the underlying library elements are implemented in VHDL. Future

releases are likely to support a mixed-language development mode where the user-

logic module is written in Verilog.

x Supports slave peripherals only

Support for master peripherals will be available in a future release.