Specifications

340 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 23: Interrupt Management
R
/* reset the timers, and clear interrupts */
XTmrCtr_mSetControlStatusReg(XPAR_MYTIMER_BASEADDR, 0,
XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );
/* start the timers */
XTmrCtr_mSetControlStatusReg(XPAR_MYTIMER_BASEADDR, 0,
XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
/* Wait for interrupts to occur */
while (1)
;
}
Example MHS File Snippet (for external interrupt signal)
PORT interrupt_in1 = interrupt_in1, DIR = IN, LEVEL = LOW, SIGIS =
INTERRUPT
BEGIN ppc405
PARAMETER INSTANCE = PPC405_i
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE DPLB = myplb
BUS_INTERFACE IPLB = myplb
PORT CPMC405CLOCK = sys_clk
PORT PLBCLK = sys_clk
PORT CPMC405CORECLKINACTIVE = net_gnd
PORT CPMC405CPUCLKEN = net_vcc
PORT CPMC405JTAGCLKEN = net_vcc
PORT CPMC405TIMERTICK = net_vcc
PORT CPMC405TIMERCLKEN = net_vcc
PORT MCPPCRST = net_vcc
PORT TIEC405DISOPERANDFWD = net_vcc
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT TIEC405MMUEN = net_gnd
PORT EICC405EXTINPUTIRQ = interrupt_in1
PORT EICC405CRITINPUTIRQ = net_gnd
PORT JTGC405TCK = JTGC405TCK
PORT JTGC405TDI = JTGC405TDI
PORT JTGC405TMS = JTGC405TMS
PORT JTGC405TRSTNEG = JTGC405TRSTNEG
PORT C405JTGTDO = C405JTGTDO
PORT C405JTGTDOEN = C405JTGTDOEN
PORT DBGC405DEBUGHALT = DBGC405DEBUGHALT
END
Example MSS File snippet
PARAMETER int_handler = global_int_handler, int_port = interrupt_in1