Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 309
UG111 (v1.4) January 30, 2004 1-800-255-7778
MicroBlaze Processor
R
Memory Speeds and Latencies
MicroBlaze requires 2 clock cycles to access on-chip Block RAM connected to the LMB for
write and 2 clock cycles for read. On chip memory connected to the OPB bus requires 3
cycles for write and 4 cycles for read. External memory access is further limited by off-chip
memory access delays for read access, resulting in 5-7 clock cycles for read. Furthermore,
memory accesses over the OPB bus may incur further latencies due to bus arbitration
overheads. As a result, instructions or data that need to be accessed quickly should be
stored in LMB memory when possible.
For more information on memory access times, see the MicroBlaze Hardware Reference
chapter.
System Address Space
MicroBlaze programs can be executed in different scenarios. Each scenario needs a
different set of system address space. The system address space is occupied by the
xmdstub or the bootstub, when debug or boot support is required. System address space is
also needed by the C-runtime routines.
Figure 22-2: Execution Scenarios
main program
main program main program
crt0.o
crt1.o crt2.o / crt3.o
xmdstub bootstub
0x00000000
0x00000000 0x00000000
(a) (b) (c)
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