Specifications

308 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 22: Address Management
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memory region only. The total amount of on-chip memory available to a MicroBlaze
system may exceed these limits. The total amount of memory available in the form of
BRAMs is also FPGA device specific. Smaller devices of a given device family provide less
BRAM than larger devices in the same device family.
Special Addresses
Every MicroBlaze system must have user writable memory present in addresses
0x00000000 through 0x00000018. These memory locations contain the addresses
MicroBlaze jumps to after a reset, interrupt, or exception event occurs. This memory can be
part of the LMB or the OPB BRAM address space. Refer to Chapter 4, “MicroBlaze
Application Binary Interface” (ABI) in the MicroBlaze Processor Reference Guide for further
details.
OPB Address Range Details
Within the OPB address space, the user can arbitrarily assign address space to on/off-chip
memory peripherals and to on/off-chip non-memory peripherals. The OPB address space
may contain holes representing regions that are not associated with any OPB peripheral.
Special linker scripts and directives may be required to control the assignment of object file
sections to address space regions.
Address Map
Figure 22-1 shows a possible address map for a MicroBlaze System. The actual address
map is defined in the MicroBlaze Hardware Specification (MHS) file. It contains an address
map specifying the addresses of LMB memory, OPB memory, External memory and
peripherals.
The address range grows from 0. At the lowest range is the LMB memory. This is followed
by the OPB memory, External Memory and the Peripherals. Some addresses in this address
space have predefined meaning. The processor jumps to address 0x0 on reset, to address
0x8 on exception, and to address 0x10 on interrupt.
Figure 22-1: A Sample Address Map for a MicroBlaze System
(Address End)
Increasing addresses
0 (Address Start)
ADDRESS SPACE MAP
Represents Holes
in Address Range
LMB Memory
On Chip OPB
Memory
External OPB
Memory
Peripherals
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