Specifications

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Chapter 22
Address Management
This chapter describes the embedded processor program address management techniques.
For advanced address space management, a discussion on linker scripts is also included in
this chapter.
This chapter contains the following sections:
x “MicroBlaze Processor”
x “PowerPC Processor”
MicroBlaze Processor
Programs and Memory
MicroBlaze users can write either C, C++ or Assembly programs, and use the Embedded
Development Kit to transform their source code into bit patterns stored in the physical
memory of a EDK System. User programs typically access local/on-chip memory, external
memory and memory mapped peripherals. Memory requirements for your programs are
specified in terms of how much memory is required for storing the instructions, and how
much memory is required for storing the data associated with the program.
MicroBlaze address space is divided between the system address space and the user
address space. In certain examples, users would need advanced address space
management, which can be done with the help of linker script, described in this chapter.
Current Address Space Restrictions
Memory and Peripherals Overview
MicroBlaze uses 32-bit addresses, and as a result it can address memory in the range zero
through 0xFFFFFFFF. MicroBlaze can access memory either through its Local Memory Bus
(LMB) port or through the On-chip Peripheral Bus (OPB). The LMB is designed to be a fast
access, on-chip block RAM (BRAM) memories only bus. The OPB represents a general
purpose bus interface to on-chip or off-chip memories as well as other non-memory
peripherals.
BRAM Size Limits
The amount of BRAM memory that can be assigned to the LMB address space or to each
instance of an OPB mapped BRAM peripheral is limited. The largest supported BRAM
memory size for Virtex/VirtexE is 16 kilobytes and for Virtex-II it is 64 kilobytes. It is
important to understand that these limits apply to each separately decoded on-chip