Specifications

268 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 16: Microprocessor Peripheral Description (MPD)
R
PORT <Mn>_busLock = M_busLock, DIR=O, BUS=MOPB
PORT
<Mn>_DBus = M_DBus, DIR=O, VEC=[0:C_OPB_DWIDTH-1], BUS=MOPB
PORT
<Mn>_request = M_request, DIR=O, BUS=MOPB
PORT
<Mn>_RNW = M_RNW, DIR=O, BUS=MOPB
PORT
<Mn>_select = M_select, DIR=O, BUS=MOPB
PORT
<Mn>_seqAddr = M_seqAddr, DIR=O, BUS=MOPB
PORT
<nOPB>_DBus = OPB_DBus, DIR=I, VEC=[0:C_OPB_DWIDTH-1], BUS=MOPB
PORT
<nOPB>_errAck = OPB_errAck, DIR=I, BUS=MOPB
PORT
<nOPB>_MGrant = OPB_MGrant, DIR=I, BUS=MOPB
PORT
<nOPB>_retry = OPB_retry, DIR=I, BUS=MOPB
PORT
<nOPB>_timeout = OPB_timeout, DIR=I, BUS=MOPB
PORT
<nOPB>_xferAck = OPB_xferAck, DIR=I, BUS=MOPB
Slave OPB Ports
For interconnection to the OPB, all slaves must provide the following connections:
PORT <Sln>_DBus = Sl_DBus, DIR=O, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPB
PORT
<Sln>_errAck = Sl_errAck, DIR=O, BUS=SOPB
PORT
<Sln>_retry = Sl_retry, DIR=O, BUS=SOPB
PORT
<Sln>_toutSup = Sl_toutSup, DIR=O, BUS=SOPB
PORT
<Sln>_xferAck = Sl_xferAck, DIR=O
PORT
<nOPB>_ABus = OPB_ABus, DIR=I, VEC=[0:C_OPB_AWIDTH-1], BUS=SOPB
PORT
<nOPB>_BE = OPB_BE, DIR=I, VEC=[0:C_OPB_DWIDTH/8-1], BUS=SOPB
PORT
<nOPB>_DBus = OPB_DBus, DIR=I, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPB
PORT
<nOPB>_RNW = OPB_RNW, DIR=I, BUS=SOPB
PORT
<nOPB>_select = OPB_select, DIR=I, BUS=SOPB
PORT
<nOPB>_seqAddr = OPB_seqAddr, DIR=I, BUS=SOPB
Master PLB Ports
For interconnection to the PLB, all masters must provide the following connections:
PORT <Mn>_ABus = M_ABus, DIR=O, VEC=[0:C_PLB_AWIDTH-1], BUS=MPLB
PORT <Mn>_BE = M_BE, DIR=O, VEC=[0:C_PLB_DWIDTH/8-1], BUS=MPLB
PORT <Mn>_RNW = M_RNW, DIR=O, BUS=MPLB
PORT
<Mn>_abort = M_abort, DIR=O, BUS=MPLB
PORT <Mn
>_busLock = M_busLock, DIR=O, BUS=MPLB
PORT <Mn
>_compress = M_compress, DIR=O, BUS=MPLB
PORT <Mn
>_guarded = M_guarded, DIR=O, BUS=MPLB
PORT <Mn>_lockErr = M_lockErr, DIR=O, BUS=MPLB
PORT <Mn>_MSize = M_MSize, DIR=O, VEC=[0:1], BUS=MPLB
PORT <Mn>_ordered = M_ordered, DIR=O, BUS=MPLB
PORT <Mn>_priority = M_priority, DIR=O, VEC=[0:1], BUS=MPLB
PORT <Mn>_rdBurst = M_rdBurst, DIR=O, BUS=MPLB
PORT
<Mn>_request = M_request, DIR=O, BUS=MPLB
PORT
<Mn>_size = M_size, DIR=O, VEC=[0:3], BUS=MPLB
PORT
<Mn>_type = M_type, DIR=O, VEC=[0:2], BUS=MPLB
PORT <Mn>_wrBurst = M_wrBurst, DIR=O, BUS=MPLB
PORT <Mn>_wrDBus = M_wrDBus, DIR=O, VEC=[0:C_PLB_DWIDTH-1], BUS=MPLB
PORT <nPLB>_MAddrAck = PLB_MAddrAck, DIR=I, BUS=MPLB
PORT <nPLB>_MBusy = PLB_MBusy, DIR=I, BUS=MPLB
PORT <nPLB>_MErr = PLB_MErr, DIR=I, BUS=MPLB
PORT <nPLB>_MRdBTerm = PLB_MRdBTerm, DIR=I, BUS=MPLB
PORT <nPLB>_MRdDAck = PLB_MRdDAck, DIR=I, BUS=MPLB
PORT <nPLB>_MRdDBus = PLB_MRdDBus, DIR=I, VEC=[0:C_PLB_DWIDTH-1],
BUS=MPLB
PORT <nPLB>_MRdWdAddr = PLB_MRdWdAddr, DIR=I, VEC=[0:3], BUS=MPLB