Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 267
UG111 (v1.4) January 30, 2004 1-800-255-7778
Reserved Port Connections
R
LMB - Clock and Reset
PORT LMB_Clk = “”, DIR=I, SIGIS=CLK
PORT LMB_Rst = LMB_Rst, DIR=I
OPB - Clock and Reset
PORT OPB_Clk = “”, DIR=I, SIGIS=CLK
PORT OPB_Rst = OPB_Rst, DIR=I
PLB - Clock and Reset
PORT PLB_Clk = “”, DIR=I, SIGIS=CLK
PORT PLB_Rst = PLB_Rst, DIR=I
Notice that the clock port has no default value. The clock port is an input to the bus and is
assigned by the user in the MHS. Therefore, all peripherals on the bus must also be treated
as a user input port. If a default value were given to LMB_Clk, OPB_Clk, or PLB_Clk, this
would not match the user defined clock in the MHS, and the EDK tools would consider
this a short in the system, and tie-off the sourceless ports.
The reset port which is an output from the bus, and has a default value. All peripherals on
the bus share the same default LMB_Rst, OPB_Rst, or PLB_Rst. The user input to the bus is
SYS_Rst which has no default value.
Slave DCR Ports
For interconnection to the DCR, all slaves must provide the following connections:
PORT <Sln>_dcrDBus = Sl_dcrDBus, DIR=O, VEC=[0:C_DCR_DWIDTH-1],
BUS=SDCR
PORT
<Sln>_dcrAck = Sl_dcrAck, DIR=O, BUS=SDCR
PORT
<nDCR>_ABus = DCR_ABus, DIR=I, VEC=[0:C_DCR_AWIDTH-1], BUS=SDCR
PORT
<nDCR>_Sl_DBus = DCR_Sl_DBus, DIR=I, VEC=[0:C_DCR_DWIDTH-1],
BUS=SDCR
PORT <nDCR>_Read = DCR_Read, DIR=I, BUS=SDCR
PORT
<nDCR>_Write = DCR_Write, DIR=I, BUS=SDCR
Slave LMB Ports
For interconnection to the LMB, all slaves must provide the following connections:
PORT <Sln>_DBus = Sl_DBus, DIR=O, VEC=[0:C_LMB_DWIDTH-1], BUS=SLMB
PORT
<Sln>_Ready = Sl_Ready, DIR=O, BUS=SLMB
PORT <nLMB>_ABus = LMB_ABus, DIR=I, VEC=[0:C_LMB_AWIDTH-1], BUS=SLMB
PORT <nLMB>_ReadStrobe = LMB_ReadStrobe, DIR=I, BUS=SLMB
PORT <nLMB>_AddrStrobe = LMB_AddrStrobe, DIR=I, BUS=SLMB
PORT <nLMB>_WriteStrobe = LMB_WriteStrobe, DIR=I, BUS=SLMB
PORT <nLMB>_WriteDBus = LMB_WriteDBus, DIR=I, VEC=[0:C_LMB_DWIDTH-1],
BUS=SLMB
PORT <nLMB>_BE = LMB_BE, DIR=I, VEC=[0:C_LMB_DWIDTH/8-1], BUS=SLMB
Master OPB Ports
For interconnection to the OPB, all masters must provide the following connections:
PORT <Mn>_ABus = M_ABus, DIR=O, VEC=[0:C_OPB_AWIDTH-1], BUS=MOPB
PORT <Mn>_BE = M_BE, DIR=O, VEC=[0:C_OPB_DWIDTH/8-1], BUS=MOPB