Specifications

266 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 16: Microprocessor Peripheral Description (MPD)
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C_PLB_MID_WIDTH
The C_PLB_MID_WIDTH parameter defines the PLB master ID width in bits. This is
determined by the number of PLB masters as shown in the following table:
This parameter is automatically populated by the EDK tools.
Format
PARAMETER C_PLB_MID_WIDTH = <num>, DT=integer
Where <num> is an integer value.
C_PLB_NUM_MASTERS
The C_PLB_NUM_MASTERS parameter defines the number of PLB masters on the bus.
This parameter is automatically populated by the EDK tools.
Format
PARAMETER C_PLB_NUM_MASTERS = <num>, DT=integer
Where <num> is an integer value.
C_PLB_NUM_SLAVES
The C_PLB_NUM_SLAVES parameter defines the number of PLB slaves on the bus. This
parameter is automatically populated by the EDK tools.
Format
PARAMETER C_PLB_NUM_SLAVES = <num>, DT=integer
Where <num> is an integer value.
Reserved Port Connections
Connectivity of the DCR, LMB, OPB and PLB busses to peripherals is done through a
common set of signal connections.
Clock and Reset Ports
For interconnection to the clock and reset ports:
Table 16-21: C_PLB_MID_WIDTH Calculation
C_PLB_NUM_MASTERS
(Number of PLB Masters)
C_PLB_MID_WIDTH
0 to 2 1
3 to 4 2
5 to 8 3
9 to 16 4