Specifications

260 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 16: Microprocessor Peripheral Description (MPD)
R
PLB Master Inputs
For interconnection to the PLB, all masters must provide the following inputs:
<nPLB>_MAddrAck
<nPLB>_MBusy
<nPLB>_MErr
<nPLB>_MRdBTerm
<nPLB>_MRdDAck
<nPLB>_MRdDBus
<nPLB>_MRdWdAddr
<nPLB>_MRearbitrate
<nPLB>_MWrBTerm
<nPLB>_MWrDAck
<nPLB>_MSSize
Where <nPLB> is a meaningful name or acronym for the master input. An additional
requirement on <nPLB> is that the last three characters must contain the string, “PLB”
(upper or lower case or mixed case).
iPLB_MBusy
PLB_MBusy
bus1_PLB_MBusy
Slave PLB Ports
Naming conventions should be followed for that part of the identifier following the last
underscore in the name.
PLB Slave Outputs
For interconnection to the PLB, all slaves must provide the following outputs:
<Sln>_addrAck
<Sln>_MErr
<Sln>_MBusy
<Sln>_rdBTerm
<Sln>_rdComp
<Sln>_rdDAck
<Sln>_rdDBus
<Sln>_rdWdAddr
<Sln>_rearbitrate
<Sln>_SSize
<Sln>_wait
<Sln>_wrBTerm
<Sln>_wrComp
<Sln>_wrDAck
Where <Sln> is a meaningful name or acronym for the slave output. An additional
requirement on <Sln> is that it must not contain the string, “PLB” (upper or lower case or
mixed case), so that slave outputs will not be confused with bus outputs.
tmr_addrAck
uart_addrAck
intc_addrAck
PLB Slave Inputs
For interconnection to the PLB, all slaves must provide the following inputs:
<nPLB>_ABus
<nPLB>_BE