Specifications

256 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 16: Microprocessor Peripheral Description (MPD)
R
Format
PORT PAR="", DIR=INOUT, THREE_STATE=FALSE, IOB_STATE=BUF
For output ports, the default value is FALSE. For inout ports, the default value is TRUE.
Please see the “3-state (InOut) Signals” section about designing tri-state signals at the HDL
level.
VEC
The vector width of a signal is specified by the VEC keyword.
Format
PORT mysignal = “”, DIR=INPUT, VEC=[A:B]
Where A and B are positive integer expressions.
Port Naming Conventions
This section provides naming conventions for bus interface signal names. These
conventions are flexible to accommodate embedded processor systems that have more
than one bus interface and more than one bus interface port per component.
The names must be HDL (VHDL or Verilog) compliant. As with any language, VHDL and
Verilog have certain naming rules and conventions that you must follow.
Global Ports
The names for the global ports of a peripheral (such as clock and reset signals) are
standardized. You can use any name for other global ports (such as the interrupt signal).
LMB - Clock and Reset
LMB_Clk
LMB_Rst
OPB - Clock and Reset
OPB_Clk
OPB_Rst
PLB - Clock and Reset
PLB_Clk
PLB_Rst
Slave DCR Ports
Naming conventions should be followed for that part of the identifier following the last
underscore in the name.
DCR Slave Outputs
For interconnection to the DCR, all slaves must provide the following outputs:
<Sln>_dcrDBus
<Sln>_dcrAck