Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 239
UG111 (v1.4) January 30, 2004 1-800-255-7778
Option
R
(double word) wide and thus has ADDR_SLICE=28. The OPB data bus is 32 bits (word)
wide and thus has ADDR_SLICE=29.
ALERT
A message alert for the IP core is specified with the ALERT keyword.
Format
OPTION ALERT = “This belongs to Xilinx”
ARCH_SUPPORT
List of supported FPGA architectures. Valid values: all, spartan2, spartan2e, spartan3,
virtex, virtexe, virtex2, virtex2p. Default is ALL. Supports a colon “:” separated list of
elements. But, may also take a single element.
Format
OPTION ARCH_SUPPORT = virtex2:spartan2e
Format
OPTION ARCH_SUPPORT = virtex2
AWIDTH
The address width is specified by the AWIDTH keyword.
Format
OPTION AWIDTH = 32
BUS_STD
Define bus standard of BUS or BUS_ARBITER cores.
Format
OPTION BUS_STD = value
Where value is either DCR, FSL, LMB, OPB, or PLB. No default.
CORE_STATE
The state of the IP core is specified with the CORE_STATE keyword.
Format
OPTION CORE_STATE = ACTIVE
The following table lists CORE_STATE values:
Table 16-5: CORE_STATE Values
CORE_STATE Definition
ACTIVE Core is active (full uninhibited use) by EDK (default)
DEPRECATED Core is deprecated. EDK tools allow use of core, but issues a
warning that the core is deprecated