Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 237
UG111 (v1.4) January 30, 2004 1-800-255-7778
Option
R
Option Keywords
An option can have the following keywords:
Table 16-4: Option Keywords
Keyword Values Default Definition
ADDR_SLICE integer No Default Address slice of BRAM controller
ALERT string No Default Alert message
ARCH_SUPPORT string ALL List of supported FPGA architectures
AWIDTH integer No Default Address width
BUS_STD DCR
DSOCM
FSL
ISOCM
LMB
OPB
PLB
No Default Define bus standard of BUS components
CORE_STATE ACTIVE
DEPRECATED
DEVELOPMENT
OBSOLETE
ACTIVE Core state
DESC string No Default Allows a short description of the core to be
displayed by the GUI tools
DWIDTH integer No Default Data width
HDL BOTH
VERILOG
VHDL
VHDL HDL design availability.
IMP_NETLIST TRUE
FALSE
FALSE Synthesize HDL to a hardware
implementation netlist using XST synthesis
IP_GROUP ALLIANCE
INFRASTRUCTURE
LOGICORE
REFERENCE
USER
USER Core group classification
IPLEVEL_DRC_PROC string No Default Tcl entry point for the IP-level DRC routine.
Currently, unsupported.