Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 233
UG111 (v1.4) January 30, 2004 1-800-255-7778
Bus Interface
R
BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR=0xFFFFFFFF, DT=std_logic_vector, MIN_SIZE=0x100, BUS=SOPB
PARAMETER C_HIGHADDR=0x00000000, DT = std_logic_vector, BUS=SOPB
PARAMETER C_OPB_DWIDTH=32, DT=integer, BUS=SOPB
PARAMETER C_OPB_AWIDTH=32, DT=integer, BUS=SOPB
PARAMETER C_GPIO_WIDTH=32, DT=integer
PARAMETER C_ALL_INPUTS=0, DT=integer
## Ports
PORT OPB_Clk = “”, DIR=IN, SIGIS=CLK, BUS=SOPB
PORT OPB_Rst = OPB_Rst, DIR=IN, BUS=SOPB
PORT OPB_ABus = OPB_ABus, DIR=IN, VEC=[0:C_OPB_AWIDTH-1], BUS=SOPB
PORT OPB_BE = OPB_BE, DIR=IN, VEC=[0:C_OPB_DWIDTH/8-1], BUS=SOPB
PORT OPB_DBus = OPB_DBus, DIR=IN, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPB
PORT OPB_RNW = OPB_RNW, DIR=IN, BUS=SOPB
PORT OPB_select = OPB_select, DIR=IN, BUS=SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR=IN, BUS=SOPB
PORT GPIO_DBus = Sl_DBus, DIR=OUT, VEC=[0:C_OPB_DWIDTH-1], BUS=SOPB
PORT GPIO_errAck = Sl_errAck, DIR = OUT, BUS=SOPB
PORT GPIO_retry = Sl_retry, DIR = OUT, BUS=SOPB
PORT GPIO_toutSup = Sl_toutSup, DIR=OUT, BUS=SOPB
PORT GPIO_xferAck = Sl_xferAck, DIR=OUT, BUS=SOPB
PORT GPIO_IO = “”, DIR=INOUT, VEC=[0:C_GPIO_WIDTH-1], ENABLE=MULT
END
Bus Interface
A bus interface is a grouping of interface ports which are related.
Several components often have many of the same ports, requiring redundant port
declaration for each component. Every component connected to a OPB bus, for example,
must have the same ports defined and connected together.
A bus interface provides a high level of abstraction for component connectivity of a
common interface. Components can use a bus interface the same as if it were a single port.
In its simplest form, a bus interface can be considered a bundle of signals.