Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 229
UG111 (v1.4) January 30, 2004 1-800-255-7778
Design Considerations
R
Concatenation is done on A, B, C, and D connecting to port Y of [7:0]. This maps to the
following: Y[7]=A, Y[6]=B[1], Y[5]=B[0], Y[4]=C, Y[3]=D[0], Y[2]=D[1], Y[1]=D[2], and
Y[0]=D[3].
Concatenation is also useful for extending a vector’s length. Use 0b denotation to define a
binary constant or 0x for a hex constant. An underscore (_) can be used for readability. For
example, given the following top-level port:
PORT E = E, DIR=INPUT, VEC=[1:0]
PORT Z = 0b00 & E, DIR=OUTPUT, VEC=[0:3]
Where the (&) operator is being used to extend the signal E to 4 bits. This maps to the
following: Z[0]=0b0, Z[1]=0b0, Z[2]=E[1], and Z[3]=E[0].
Internal vs. External Signals
By default, all signals defined between a BEGIN-END block are internal signals.
External signals are available through the port-declaration of the top-level module. Use the
PORT command outside of a BEGIN-END block to declare the external signal.
External Interrupt Signals
For internal interrupts, each interruptible peripheral instance defines an interrupt signal
locally.
For external interrupts, use the PORT command outside of a BEGIN-END block to declare
the external signal and define the interrupt sensitivity.
Format
PORT my_int1 = my_int1, LEVEL=HIGH, DIR=INPUT