Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 227
UG111 (v1.4) January 30, 2004 1-800-255-7778
Local Port
R
Where the value is either CLK, INTERRUPT, or RST. The following table lists SIGIS usage:
VEC
The vector width of a signal is specified by the VEC keyword.
Format
PORT mysignal = "", DIR=I, VEC=[A:B]
Where A and B are positive integer expressions.
Local Port
A local port is a port defined between a BEGIN-END block. A local port does not have
keywords.
Design Considerations
This section provides general design considerations.
Defining Memory Size
Memory sizes are based on C_BASEADDR and C_HIGHADDR settings. Use the following
format when defining memory size:
PARAMETER C_HIGHADDR= 0xFFFF00FF
PARAMETER C_BASEADDR= 0xFFFF0000
All memory sizes must be 2
N
where N is a positive integer, and 2
N
boundary overlaps are
not allowed.
Table 15-6: SIGIS Usage
SIGIS Usage
CLK x XPS
i Display all clock signals
x PlatGen
i If system is the top-level, then clock buffer
insertion is done on all input clocks of the
system
i For all bus peripherals, the clock signals are
automatically connected to the clock input of
the bus
INTERRUPT
x XPS
i Display all interrupt signals
x PlatGen
i Encodes the priority interrupt vector
RST
x XPS
i Display all reset signals