Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 213
UG111 (v1.4) January 30, 2004 1-800-255-7778
XMD Internal Tcl Commands
R
x xcontinue target [addr]
Continue execution from the current PC or from the optional address argument.
x xcycle_step target [cycles]
Cycle step through one clock cycle of PowerPC ISS. If cycles is specified, then step
“cycles” number of clock cycles. Note: This command is only for PowerPC ISS target.
x xstep target
Single step one MicroBlaze instruction. If the PC is at an IMM instruction the next
instruction is executed as well. During a single step, interrupts are disabled by
keeping the BIP flag set. Use xcontinue with breakpoints to enable interrupts while
debugging.
x xreset target [reset type]
Reset target. Optionally provide target specific reset types like signals mentioned
in Table 13-2.
x xbreakpoint target addr <sw|hw> [<Hardware Breakpoint ID>]
Set a breakpoint at the given address. Note - Breakpoints on instructions
immediately following imm instruction can lead to undefined results for xmdstub
target. The Hardware Breakpoint ID is valid only for the MicroBlaze MDM target,
where this is used to set a specific breakpoint.
x xremove target addr [<Hardware Breakpoint ID>]
Remove breakpoint at given address.
x xlist target
List all the breakpoint addresses.
x xdisassemble inst
Disassemble and display one 32-bit instruction.
x xsignal target signal
Send a signal to a hardware target. This is only supported by the JTAG UART
when the debug signals for Processor Break, Reset and System reset are connected
to MicroBlaze and the OPB bus. Platform Generator automatically connects these
signals by default of the implicit name matching in the respective MPD files.
Supported signals are listed in Table 13-2.
Table 13-2: XMD MicroBlaze Hardware target signals
Signal Name (value) Description
Processor Break (0x20)
Raises the Brk signal on MicroBlaze using the JTAG
UART Ext_Brk signal. It sets the Break-in-Progress (BIP)
flag on MicroBlaze and jumps to addr 0x18
Non-maskable Break (0x10) Similar to the Break signal but works even while the BIP
flag is already set. Refer the MicroBlaze ISA
documentation for more information about the BIP flag.
System Reset (0x40) Resets the entire system by sending an OPB Rst using the
JTAG UART Debug_SYS_Rst signal.
Processor Reset (0x80) Resets MicroBlaze using the JTAG UART Debug_Rst
signal.