Specifications

190 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)

1-800-255-7778 UG111 (v1.4) January 30, 2004

Chapter 13: Xilinx Microprocessor Debugger (XMD)

x isocmsize <ISOCM size>

Size of the ISBRAM memory connected to the ISOCM interface

x isocmdcrstartadr <ISOCM DCR address>

DCR address corresponding to the ISOCM interface specified using the

TIEISOCMDCRADDR signals on PowerPC

x tlbstartadr <TLB start address>

Start address for reading and writing the Translation Look-aside Buffer

x dcrstartadr <DCR start address>

Start address for reading and writing the Device Control Registers. Using this

option, the entire DCR address space (2

addresses) can be mapped to addresses

starting from <dcrstartadr> for debugging purposes from XMD and GDB

PowerPC Target Requirements

There are two possible methods for xmd to connect to the PowerPC 405 processors over a

JTAG connection. The requirements for each of these methods are described below.

1. Debug connection using the JTAG port of the Virtex-II Pro FPGA

If the JTAG ports of the PowerPC processors are connected to the JTAG port of the

FPGA internally using the JTAGPPC primitive, then xmd can connect to any of the

PowerPC processors inside the FPGA, as shown in Figure 13-2. Please refer to the

“Virtex-II Pro PPC405 JTAG Debug Port“ section in the PowerPC 405 Processor Block

Reference Guide for more information about this debug setup. NOTE that there is a core

named jtagppc_cntlr in EDK that helps in setting up this connection.

2. Debug connection using user IO pins connected to the JTAG port of the PowerPC

If the JTAG ports of the PowerPC processors are brought out of the FPGA using user

IO pins, xmd can directly connect to the PowerPC for debugging. Please refer to the

“Virtex-II Pro PPC405 JTAG Debug Port“ section in the PowerPC 405 Processor Block

Reference Guide for more information about this debug setup.