Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 189
UG111 (v1.4) January 30, 2004 1-800-255-7778
PowerPC Target
R
In the case of xilinx_svffile, the JTAG commands are written into a file specified by
the fname option
x port <parallel port name>
Valid arguments for port are lpt1, lpt2
x fname <filename>
Filename for creating the SVF file
JTAG chain options
x partname <devicename>
Name of the device
x devicenr <device position>
Position of the device in the JTAG chain
x irlength <length of the JTAG Instruction Register>
Length of the IR register of the device. This information can be found in the device
BSDL file.
x idcode <device idcode>
JTAG Idcode of the device
PPC405 options
x devicenr <PowerPC device position>
Position of the VirtexIIPro device containing the PowerPC, in the JTAG chain
x cpunr <CPU Number>
ID of the specific PowerPC to be debugged in a VirtexIIPro containing multiple
PowerPC processors
The following options allow users to map special PowerPC features like ISOCM, Caches,
TLB, DCR registers, etc. to unused memory addresses and then from the debugger access
it as memory addresses. This is helpful for reading and writing to these registers/memory
from GDB or XMD. Note that, these options do not create any real memory mapping in
hardware.
x icachestartadr <I-Cache start address>
Start address for reading or writing the instruction cache contents
x dcachestartadr <D-Cache start address>
Start address for reading or writing the data cache contents
x itagstartadr <I-Cache start address>
Start address for reading or writing the instruction cache tags
x dtagstartadr <D-Cache start address>
Start address for reading or writing the data cache tags
x isocmstartadr <ISOCM start address>
Start address for the ISOCM