Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 157
UG111 (v1.4) January 30, 2004 1-800-255-7778
VHDL Peripheral Definitions
R
port (
PAR_I : in std_logic;
PAR_O : out std_logic;
PAR_T : out std_logic;
);
attribute THREE_STATE : string;
attribute THREE_STATE of PAR_I:signal is "FALSE";
attribute THREE_STATE of PAR_O:signal is "FALSE";
attribute THREE_STATE of PAR_T:signal is "FALSE";
end entity Peripheral;
IOB_STATE Attribute
The IOB_STATE attribute identifies ports that instantiate or infer IOB primitives.
Format
entity Peripheral is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000"
);
port (
DDR_Addr : out std_logic
);
attribute IOB_STATE : string;
attribute IOB_State of DDR_Addr:signal is "BUF";
end entity Peripheral;
The values are BUF, INFER, or REG. The default is INFER.
When a port has an IOB register (IOB_STATE=REG) or requires an IOB primitive
(IOB_STATE=INFER), PlatGen instantiates an IOB buffer. When a port has an IOB buffer
(IOB_STATE=BUF), PlatGen does not instantiate an IOB primitive.
SIGIS Attribute
The class of a signal is specified by the SIGIS option.
Format
entity Peripheral is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000"
);
port (
Interrupt_sig : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of Interrupt_sig:signal is "INTR_LEVEL_HIGH";
end entity Peripheral;
Where the SIGIS value can have the following values
x CLK : indicating it is a Clock signal
x INTR_LEVEL_HIGH : indicating it is an Interrupt signal with Level High Sensitivity