Specifications

156 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 8: Platform Specification Utility
R
Signal-level VHDL Attributes for Automation Support
THREE_STATE Attribute
The THREE_STATE attribute enables/disables tri-state IOB buffer insertion. When this
attribute is not specified, PsfUtility automatically generates a THREE_STATE attribute set
to true for all signals in the HDL that end with _I, _O and _T.
Format
entity Peripheral is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector(0 to 31) := X"00000000"
);
Table 8-4: Signal-level VHDL Attributes
Attribute Type Values Default PsfUtil Automation Definition
THREE_STATE string TRUE
FALSE
X Automatic inference
based on signal
naming conventions
3-state expansion
(equivalent to the
3STATE parameter in
MPD file)
IOB_STATE string BUF
INFER
REG
INFER - Identifies ports that
instantiate or infer IOB
primitives
SIGIS string CLK
INTR_LEVEL_LOW
INTR_LEVEL_HIGH
INTR_EDGE_RISING
INTR_EDGE_FALLING
RST
X - Signal classification
ENDIAN string BIG, LITTLE BIG Semi-automatic
inference when
ranges can be
resolved at compile
time
Specifies endianess of
signals.
INITIALVALL string VCC, GND GND - defines initial value of
signal if unconnected
BUSIF string - - Automatic inference
based on signal
naming conventions
specifies bus interfaces
associated to signal.
SIGVAL string - - Automatic inference
for bus interface
signals based on
signal naming
conventions
specifies default signal
connector names to
connect to signal