Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 149
UG111 (v1.4) January 30, 2004 1-800-255-7778
VHDL Peripheral Definitions
R
ADDR_SLICE Attribute
The address slice position supported by the BRAM controller is specified by the
ADDR_SLICE attribute.
Format
attribute ADDR_SLICE : integer;
attribute ADDR_SLICE of Peripheral:entity is 29;
Used only by components of SPECIAL=BRAM_CNTLR.
AWIDTH Attribute
The address width supported by the BRAM controller is specified by the AWIDTH
attribute.
Format
attribute AWIDTH : integer;
attribute AWIDTH of Peripheral:entity is 32;
Used only by components of SPECIAL=BRAM_CNTLR.
ALERT Attribute
A message alert for the IP core is specified with the ALERT attribute. The character \n may
be used as a newline character within the ALERT string.
Format
attribute ALERT : string;
attribute ALERT of Peripheral:entity is
"This belongs to Xilinx.";
BUSID Attribute
The BUSID attribute is used to define all of the Bus Identifiers that are used in the signal list
and generic list. Any bus that uses the <BI> field in the naming of its signals must have a
corresponding BUSID attribute so that the signal names can be parsed correctly. The
format of the BUSID string is:
“<BI
1
>:<interface_type>[:<interface_type>][,<BI
2
>:<interface_type>[:<interface_type>]”
where as many Bus Identifiers as required can be defined, each with multiple interface
types (for signals that are shared between more than one interface). <interface_type> is one
of:
DCR_SLAVE, LMB_SLAVE, OPB_SLAVE, PLB_SLAVE, OPB_MASTER, PLB_MASTER, or
OPB_MASTER_SLAVE
Format
Examples:
attribute BUSID : string;
attribute BUSID of Peripheral:entity is
"M:OPB_SLAVE";
attribute BUSID : string;