Specifications
146 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 8: Platform Specification Utility
R
PLB Slave Outputs
For interconnection to the PLB, all slaves must provide the following outputs:
<BI><Sln>_addrAck : out std_logic;
<BI><Sln>
_MErr  : out std_logic_vector(0 to C_<BI>PLB_NUM_MASTERS-1);
<BI><Sln>_MBusy : out std_logic_vector(0 to C_<BI>PLB_NUM_MASTERS-1);
<BI><Sln>_rdBTerm : out std_logic;
<BI><Sln>_rdComp : out std_logic;
<BI><Sln>_rdDAck : out std_logic;
<BI><Sln>_rdDBus 
: out std_logic_vector(0 to C_<BI>PLB_DWIDTH-1);
<BI><Sln>_rdWdAddr : out std_logic_vector(0 to 3);
<BI><Sln>_rearbitrate : out std_logic;
<BI><Sln>_SSize : out std_logic(0 to 1);
<BI><Sln>_wait : out std_logic;
<BI><Sln>_wrBTerm : out std_logic;
<BI><Sln>_wrComp : out std_logic;
<BI><Sln>_wrDAck : out std_logic;
Examples:
Tmr_addrAck : out std_logic;
Uart_addrAck : out std_logic;
Intc_addrAck : out std_logic;
PLB Slave Inputs
For interconnection to the PLB, all slaves must provide the following inputs:
<BI><nPLB>_Clk : in std_logic;
<BI><nPLB>_Rst : in std_logic;
<BI><nPLB>_ABus : in std_logic_vector(0 to C_<BI>PLB_AWIDTH-1);
<BI><nPLB>_BE : in std_logic_vector(0 to C_<BI>PLB_DWIDTH/8-1);
<BI><nPLB>_PAValid : in std_logic;
<BI><nPLB>_RNW : in std_logic;
<BI><nPLB>_abort : in std_logic;
<BI><nPLB>_busLock : in std_logic;
<BI><nPLB>_compress : in std_logic;
<BI><nPLB>_guarded : in std_logic;
<BI><nPLB>_lockErr : in std_logic;
<BI><nPLB>_masterID : in std_logic_vector(0 to C_<BI>PLB_MID_WIDTH-1);
<BI><nPLB>_MSize : in std_logic_vector(0 to 1);
<BI><nPLB>_ordered : in std_logic;
<BI><nPLB>_pendPri : in std_logic_vector(0 to 1);
<BI><nPLB>_pendReq : in std_logic;
<BI> 
_reqpri : in std_logic_vector(0 to 1);
<BI><nPLB>_size : in std_logic_vector(0 to 3);
<BI><nPLB>_type : in std_logic_vector(0 to 2);
<BI><nPLB>_rdPrim : in std_logic;
<BI><nPLB>_SAValid : in std_logic;
<BI><nPLB>_wrPrim : in std_logic;
<BI><nPLB>_wrBurst : in std_logic;
<BI><nPLB>_wrDBus : in std_logic_vector(0 to C_<BI>PLB_DWIDTH-1);
<BI><nPLB>_rdBurst : in std_logic;
Examples:
PLB_size : in std_logic_vector(0 to 3);
IPLB_size : in std_logic_vector(0 to 3);
DPLB_size : in std_logic_vector(0 to 3);










