Specifications

144 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 8: Platform Specification Utility
R
<BI><Sln>_errAck : out std_logic;
<BI><Sln>_retry : out std_logic;
<BI><Sln>_toutSup : out std_logic;
<BI><Sln>_xferAck : out std_logic;
Examples:
IM_request : out std_logic;
Bridge_request : out std_logic;
O2Ob_request : out std_logic;
OPB Master/Slave Inputs
For interconnection to the OPB, all master/slaves must provide the following inputs:
<BI><nOPB>_ABus : in std_logic_vector(0 to C_<BI>OPB_AWIDTH-1);
<BI><nOPB>_BE : in std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1);
<BI><nOPB>_Clk : in std_logic;
<BI><nOPB>_DBus : in std_logic_vector(0 to C_<BI>OPB_DWIDTH-1);
<BI><nOPB>_errAck : in std_logic;
<BI><nOPB>_MGrant : in std_logic;
<BI><nOPB>_retry : in std_logic;
<BI><nOPB>_RNW : in std_logic;
<BI><nOPB>_Rst : in std_logic;
<BI><nOPB>_select : in std_logic;
<BI><nOPB>_seqAddr : in std_logic;
<BI><nOPB>_timeout : in std_logic;
<BI><nOPB>_xferAck : in std_logic;
Examples:
IOPB_DBus : in std_logic_vector(0 to C_IOPB_DWIDTH-1);
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
Bus1_OPB_DBus : in std_logic_vector(0 to C_Bus1_OPB_DWIDTH-1);
Master PLB Ports
Master PLB ports must follow these naming conventions:
x <Mn> is a meaningful name or acronym for the master output. <Mn> must not
contain the string, “PLB” (upper or lower case or mixed case), so that master outputs
will not be confused with bus outputs.
x <nPLB> is a meaningful name or acronym for the master input. The last three
characters of
<nOPB> must contain the string, “PLB” (upper or lower case or mixed
case).
x <BI> is a Bus Identifier; it is optional for peripherals with a single master PLB port,
and required for peripherals with multiple master PLB ports. <BI> must not contain
the string, “PLB” (upper or lower case or mixed case). For peripherals with multiple
master PLB ports, the <BI> strings must be unique for each bus interface.
x If <BI> is present, then <Mn> is optional.
PLB Master Outputs
For interconnection to the PLB, all masters must provide the following outputs:
<BI><Mn>_ABus : out std_logic_vector(0 to C_<BI>PLB_AWIDTH-1);
<BI><Mn>_BE : out std_logic_vector(0 to C_<BI>PLB_DWIDTH/8-1);
<BI><Mn>_RNW : out std_logic;
<BI><Mn>_abort : out std_logic;