Specifications

Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 143
UG111 (v1.4) January 30, 2004 1-800-255-7778
VHDL Peripheral Definitions
R
OPB Slave Inputs
For interconnection to the OPB, all slaves must provide the following inputs:
<BI><nOPB>_ABus : in std_logic_vector(0 to C_<BI>OPB_AWIDTH-1);
<BI><nOPB>_BE : in std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1);
<BI><nOPB>_Clk : in std_logic;
<BI><nOPB>_DBus : in std_logic_vector(0 to C_<BI>OPB_DWIDTH-1);
<BI><nOPB>_Rst : in std_logic;
<BI><nOPB>_RNW : in std_logic;
<BI><nOPB>_select : in std_logic;
<BI><nOPB>_seqAddr : in std_logic;
Examples:
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);
IOPB_DBus : in std_logic_vector(0 to C_IOPB_DWIDTH-1);
Bus1_OPB_DBus : in std_logic_vector(0 to C_Bus1_OPB_DWIDTH-1);
Master/Slave OPB Ports
The signal list shown below applies to master/slave type OPB ports that attach to the same
OPB bus and share the input and output data buses. This type of bus interface is typically
used when a peripheral has both master and slave functionality (typical when DMA is
included with the peripheral) and it is advantageous for the master and slave to share the
input and output data buses.
Master/Slave OPB ports must follow these naming conventions:
x <Mn> is a meaningful name or acronym for the master output. <Mn> must not
contain the string, “OPB” (upper or lower case or mixed case), so that master outputs
will not be confused with bus outputs.
x <Sln> is a meaningful name or acronym for the slave output. <Sln> must not contain
the string, “OPB” (upper or lower case or mixed case), so that slave outputs will not
be confused with bus outputs.
x <nOPB> is a meaningful name or acronym for the slave input. The last three
characters of <nOPB> must contain the string, “OPB” (upper or lower case or mixed
case).
x <BI> is a Bus Identifier; it is optional for peripherals with a single OPB port, and
required for peripherals with multiple OPB ports (of any type). <BI> must not contain
the string, “OPB” (upper or lower case or mixed case). For peripherals with multiple
OPB ports (of any type or mix of types), the <BI> strings must be unique for each bus
interface.
x If <BI> is present, then <Sln> and <Mn> are optional.
OPB Master/Slave Outputs
For interconnection to the OPB, all master/slaves must provide the following outputs:
<BI><Sln>_ABus : out std_logic_vector(0 to C_<BI>OPB_AWIDTH-1);
<BI><Sln>_BE : out std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1);
<BI><Sln>_busLock : out std_logic;
<BI><Sln>_request : out std_logic;
<BI><Sln>_RNW : out std_logic;
<BI><Sln>_select : out std_logic;
<BI><Sln>_seqAddr : out std_logic;
<BI><Sln>_DBus : out std_logic_vector(0 to C_<BI>OPB_DWIDTH-1);