Specifications

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Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 141

UG111 (v1.4) January 30, 2004 1-800-255-7778

VHDL Peripheral Definitions

<BI><Sln>_Ready : out std_logic;

Examples:

D_Ready : out std_logic;

I_Ready : out std_logic;

LMB Slave Inputs

For interconnection to the LMB, all slaves must provide the following inputs:

<BI><nLMB>_ABus : in std_logic_vector(0 to C_<BI>LMB_AWIDTH-1);

<BI><nLMB>_AddrStrobe : in std_logic;

<BI><nLMB>_BE : in std_logic_vector(0 to C_<BI>LMB_DWIDTH/8-1);

<BI><nLMB>_Clk : in std_logic;

<BI><nLMB>_ReadStrobe : in std_logic;

<BI><nLMB>_Rst : in std_logic;

<BI><nLMB>_WriteDBus : in std_logic_vector(0 to C_<BI>LMB_DWIDTH-1);

<BI><nLMB>_WriteStrobe : in std_logic;

Examples:

LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);

DLMB_ABus : in std_logic_vector(0 to C_DLMB_AWIDTH-1);

Master OPB Ports

The signal list shown below applies to master OPB ports that are independent of slave OPB

ports. For the signal list for cores that use a combined master/slave bus interface, see XXX.

Master OPB ports must follow these naming conventions:

x <Mn> is a meaningful name or acronym for the master output. <Mn> must not

contain the string, “OPB” (upper or lower case or mixed case), so that master outputs

will not be confused with bus outputs.

x <nOBP> is a meaningful name or acronym for the master input. The last three

characters of <nOPB> must contain the string, “OPB” (upper or lower case or mixed

case).

x <BI> is a Bus Identifier; it is optional for peripherals with a single OPB port (of any

type), and required for peripherals with multiple OPB ports (of any type or mix of

types). <BI> must not contain the string, “OPB” (upper or lower case or mixed case).

For peripherals with multiple OPB ports, the <BI> strings must be unique for each bus

interface.

x If <BI> is present, then <Mn> is optional.

OPB Master Outputs

For interconnection to the OPB, all masters must provide the following outputs:

<BI><Mn>_ABus : out std_logic_vector(0 to C_<BI>OPB_AWIDTH-1);

<BI><Mn>_BE : out std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1);

<BI><Mn>_busLock : out std_logic;

<BI><Mn>_DBus : out std_logic_vector(0 to C_<BI>OPB_DWIDTH-1);

<BI><Mn>_request : out std_logic;

<BI><Mn>_RNW : out std_logic;

<BI><Mn>_select : out std_logic;

<BI><Mn>_seqAddr : out std_logic;

Examples: