Specifications

138 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)
1-800-255-7778 UG111 (v1.4) January 30, 2004
Chapter 8: Platform Specification Utility
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C_OPB_DWIDTH
The C_OPB_DWIDTH parameter defines the OPB data width. This parameter is
automatically populated by Platform Generator.
C_OPB_NUM_MASTERS
The C_OPB_NUM_MASTERS parameter defines the number of OPB masters on the bus.
This parameter is automatically populated by Platform Generator.
C_OPB_NUM_SLAVES
The C_OPB_NUM_SLAVES parameter defines the number of OPB slaves on the bus. This
parameter is automatically populated by Platform Generator.
C_PLB_AWIDTH
The C_PLB_AWIDTH parameter defines the PLB address width. This parameter is
automatically populated by Platform Generator.
C_PLB_DWIDTH
The C_PLB_DWIDTH parameter defines the PLB data width. This parameter is
automatically populated by Platform Generator.
C_PLB_MID_WIDTH
The C_PLB_MID_WIDTH parameter defines the PLB master ID width. This is set to
log2(S). This parameter is automatically populated by Platform Generator.
C_PLB_NUM_MASTERS
The C_PLB_NUM_MASTERS parameter defines the number of PLB masters on the bus.
This parameter is automatically populated by Platform Generator.
C_PLB_NUM_SLAVES
The C_PLB_NUM_SLAVES parameter defines the number of PLB slaves on the bus. This
parameter is automatically populated by Platform Generator.
Signal Naming Conventions
This section provides naming conventions for bus interface signal names. These
conventions are flexible to accommodate embedded processor systems that have more
than one bus interface and more than one bus interface port per component. A key concept
for cores with more than one bus interface port is the use of a bus identifier, which is
attached to all signals grouped together in a port as well as the parameters that are
associated with the bus interface port. The bus identifier is discussed below.
The names must be VHDL compliant. As with any language, VHDL has certain naming
rules and conventions that you must follow. Additional conventions for IP cores are:
x The first character in the name must be alphabetic and uppercase.
x The fixed part of the identifier for each signal must appear exactly as shown in the
applicable section below. Each section describes the required signal set for one type of
bus interface.