Specifications

132 www.xilinx.com Embedded System Tools Guide (EDK 6.2i)

1-800-255-7778 UG111 (v1.4) January 30, 2004

Chapter 8: Platform Specification Utility

Properties on Ports

Port Value

When signal naming conventions are followed, PsfUtility automatically connects the bus

signals to the appropriate bus connector.

DIR

This value is automatically generated by PsfUtility.

VEC

This value is automatically generated by PsfUtility.

BUSIF

When signal naming conventions are followed, PsfUtility automatically associates a BUS

with a port.

For transparent buses however, the BUSIF attribute MUST BE SPECIFIED for the port.

SIGIS (User MUST Specify)

All Clock ports that must be driven by a clock buffer must have the SIGIS attribute on the

clock ports set to CLK.

All Interrupt ports that must have a SIGIS attribute on the interrupt ports set to

INTR_LEVEL_HIGH, INTR_LEVEL_LOW, INTR_EDGE_RISING or

INTR_EDGE_FALLING based on whether the Interrupt is a Level High, Level Low, Rising

Edge or Falling Edge triggered interrupt.

IOB_STATE (User MUST Specify)

The IOB_STATE attribute must be specified if the port must be driven by an IO buffer or

THREE_STATE

All signals that have a signame_I, signame_O and signame_T names specified in the HDL

are automatically inferred as tristate signals by PsfUtility. Note that in order to propagate

other attributes (like say IOB_STATE on signame), these attributes must be specified on the

“_I” signal. The ENABLE=MULTI is automatically inferred based on the size of the

signame_T signal.

ENDIAN (User MUST specify)

For all signals that are little endian, but cannot be automatically inferred as little endian,

the user must specify the endian attribute on ports. When the range of ports cannot be

resolved (both left and right range are the same, or the ranges are based on parameters),

PsfUtility cannot resolve the Endianess automatically. For these kinds of ports, the

endianess must be specified as LITTLE if the port is little endian.