Specifications

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Memory Initialization
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After a successful simgen execution, the simulation directory contains the following files:
peripheral_wrapper.[vhd|v]
Modular simulation files for each component. Not applicable for timing models.
system_name.[vhd|v]
The top level HDL file of the design.
system_name.sdf
The Standard Delay Format file with the appropriate block and net delays from the
place and route process used only for timing simulation.
system_name.[do|sh]
Script to compile the hdl files and load the compiled simulation models in the
simulator.
Memory Initialization
If a design contains banks of memory for a system, the corresponding memory simulation
models can be initialized with data. With the -pe switch, a list of executable elf files to
associate to a given processor instance can be specified.
The compiled executable files are generated with the appropriate gcc compiler or
assembler, from corresponding C or assembly source code.
Note: Memory initialization of structural simulation models is only supported when the netlist file
has hierarchy preserved.
VHDL
For vhdl simulation models, execute SimGen with the -pe option to generate a VHDL file.
This file will contain a configuration for the system with all initialization values. For
example:
simgen system.mhs -pe mblaze executable.elf -l vhdl ...
This command generates the VHDL system configuration in the file system_init.vhd. This
file is used along with your system to initialize memory. The bram blocks connected to the
processor mblaze will contain the data in executable.elf.
Verilog
For verilog simulation models, execute SimGen with the -pe option to generate a verilog
file. This file will contain defparam constructs that initialize memory. For example:
simgen system.mhs -pe mblaze executable.elf -l verilog ...
This command generates the verilog memory initialization file system_init.v. This file is
used along with your system to initialize memory. The bram blocks connected to the
processor mblaze will contain the data in executable.elf.
Simulating Your Design
When simulating your design, there are some special considerations you need to keep in
mind such as the global reset and tristate nets. Xilinx ISE Tools provide detailed
information on how to simulate your VHDL or Verilog design. Please refer to Chapter 6,